A Standard-Cell Placement Tool for Designs with High Row Utilization

In this paper we study the correlation between wirelength and routability for standard-cell placement problem, under the fixed-die place-androute environment. We present a placement tool with better routability for designs with high row utilization. Compared to a well-known industrial placement tool, our placer produces placements with equal or better routability, 13.2% better half-perimeter wirelength, 15.3% better routed wirelength, and 9.1% less vias. Compared to a state-of-the-art academic placement tool Capo, our placer produces placements with significantly better routability, 14.5% better half-perimeter wirelength, 18.1% better routed wirelength, and 8.2% less vias. Experimental results show that purely minimizing wirelength, without congestion optimization, still improves routability and layout quality. Several novel algorithmic details are presented in the paper with experimental results. The framework and detailed implementation of our placer are described and various placement techniques are investigated. Additionally, we have built a set of benchmarks with reasonable circuit sizes and standard-cell sizes.